This invention relates in general to non-volatile memory systems and, in particular, to a non-volatile memory system with programming time control.
The memory cells or charge storage elements (the two terms used herein interchangeably) of a non-volatile memory are typically programmed one partial or complete row of cells in parallel at a time. Programming voltage pulses are applied to the selected row of memory cells until the threshold voltage of each of the selected cells in the row has been programmed to a value within a predetermined voltage range (which may or may not be the final desired state of the cell) in a programming cycle. During each programming cycle, a time sequence of programming voltage pulses of voltage level or amplitude Vpgm are applied at predetermined time intervals, such as periodic time intervals, where the amplitude of each programming pulse has been incremented by a fixed voltage step ΔVpgm (e.g. 0.2 V) compared to the amplitude of the immediately preceding programming pulse in the sequence. An example of an array of memory cells or charge storage elements that are programmed in the above manner is a NAND cell array.
In time periods between the programming voltage pulses, program-verify operations are carried out. That is, the programmed level of each charge storage element (e.g. charge storage transistor) being programmed in parallel is read after each programming pulse to determine whether it is not less than the verify voltage level to which it is being programmed. If it is determined that the threshold voltage of a given charge storage element has exceeded the verify voltage level, programming of such charge storage element is stopped by raising the voltage of the bit line to which the particular charge storage element is connected to from a low voltage (typically 0 volts) to a high or inhibit level (typically Vdd). Programming of other charge storage elements being programmed in parallel continues until they in turn reach their verify voltage levels. After each program verify operation, if there still is one or more charge storage elements being programmed in parallel whose threshold voltage still has not reached the verify voltage level, the amplitude of the programming pulse is increased by the predetermined step size and applied again to the charge storage elements being programmed in parallel, which is followed again by a program-verify operation. If after the next programming operation the increased programming pulse still has not caused the threshold voltage of all of the charge storage elements being programmed in parallel to reach the verify voltage level, the amplitude of the programming pulse is increased yet again by the same predetermined step size during the next time interval and this process is repeated until threshold voltages of all of the charge storage elements being programmed in parallel have reached the verify voltage level. This marks the end of a particular programming cycle.
As will be evident from the above description, the above programming process requires repetitively programming the cells with a programming pulse followed by a program-verify operation. This process, therefore, can be time consuming. It is, therefore, desirable for the program time for the application of each programming pulse to have a short duration so that the memory cells or charge storage elements can be programmed to the desired threshold voltages in as short a time as possible.
The time sequence of programming pulses that are used to program charge storage elements is illustrated in FIG. 2A, where 13 such consecutive pulses are shown, although it is possible to employ a larger or fewer number of pulses for programming the elements to any particular threshold voltage. The voltage pulses may start at an initial program pulse level such as 15 volts and increase by a predetermined step size such as 0.2 volts for every pulse.
In FIG. 2A, the programming pulses in the sequence used to program charge storage elements are illustrated to have substantially vertical leading and trailing edges. In practice, the pulse shape of the programming pulses is different from those shown, because a charge pump typically requires a charge-up time to increase the voltage output from a reference voltage level to the required Vpgm level, and the pulse requires a time period to decrease back to the reference level at the trailing edge of the pulse. This is illustrated in FIGS. 1 and 2B.
As shown in FIG. 1, at time t0, the charge pump starts increasing the voltage output from a starting reference level such as the ground level, and applies the output to the selected control gate line or word line. However, it is not until the time t1 that the output of the charge pump reaches the required voltage level Vpgm that is effective for altering transistor threshold voltage as shown in FIG. 1. After the output of the charge pump reaches the required voltage level at time t1, this voltage level is maintained until a time t2 which marks the end of the time period in which the output of the charge pump is maintained at the required program voltage level Vpgm. Thereafter, the charge pump output declines back to the reference level by time t3. Thus the total program time allocated for programming the control gate line or word line is the sum of two of the three time periods: t0−t1 (or T) and t1−t2, and the memory proceeds to the next program pulse or program verify after t3. The time period t0−t1 or T is the charge-up time required for the charge pump in order to deliver the required program voltage level Vpgm. The time period t1−t2 is the pulse width, which is the effective program time during which the voltage of the selected control gate line or word line is ramped up to the desired Vpgm level effective for altering the threshold voltage of charge storage elements.
Thus in reference to FIG. 2A, each of the 13 pulses labeled 1 through 13 actually has a shape similar to that shown in FIG. 1. As illustrated in FIG. 2A, the Vpgm level that is required to be delivered by the charge pump increases by ΔVpgm every time a new charge pump pulse is generated, so that the required program voltage or Vpgm level trends higher from pulse 1 to pulse 13 as shown in FIG. 2A. A higher Vpgm level requires a longer charge-up time compared to a lower Vpgm as illustrated in FIG. 2B.
In conventional designs for charge pump control, the total program time allocated for programming the selected control gate line or word line is fixed and does not change with the increasing program voltage level Vpgm required. This situation is illustrated in FIG. 2B. Thus in reference to FIGS. 2A and 2B, for pulse 1 in FIG. 2A, the voltage level required to be delivered by the charge pump at Vpgm1 is still relatively low so that charge-up time T1 is relatively short, leaving most of the fixed program time available in conventional schemes for the charge pump to ramp up the control gate line or word line to the required voltage level Vpgm1. For the pulse 5, however, the Vpgm5 level that needs to be delivered by the charge pump is higher than that for pulse 1 so that a longer charge-up time T5 is required, leaving a shorter time available for applying the ramped up voltage at Vpgm5 level to the selected control gate line or word line effective for altering the threshold voltage of the charge storage elements controlled by such line. For pulse 10, the required voltage pump pulse level Vpgm10 is even higher so that an even longer charge-up time T10 is required leaving an even smaller portion of the fixed program time available for the charge pump output at Vpgm10 for altering the threshold voltage of the charge storage elements. This means that as the required programming voltage of the charge pump pulse is increased, the effective program time or pulse width is becoming shorter and shorter and therefore less and less effective in programming the charge storage elements to reach the verify voltage level. The net result is that a larger number of programming pulses must be applied to program all the cells that are programmed in parallel. This is undesirable since it reduces performance of the memory system.
The above programming operation applies both to multi-level charge storage elements as well as binary-level charge storage elements or memory cells. An illustration of the above programming and program-verify operations to multi-level charge storage elements is described in U.S. Pat. No. 6,522,580, which is incorporated herein by reference in its entirety.
One solution to the above problem is to increase the fixed time allocated for the programming, so that even at high programming voltages, the increased program time allocated allows the charge pump output at the required high Vpgm level to stay at such level for an adequate time for altering charge storage element threshold voltages even after an increased charge-up time. As noted above, for increased performance it will be desirable to minimize the programming time of each programming cycle in which the programming pulses are applied. Since allocating a longer programming time is needed only at high programming voltages (i.e. at high Vpgm levels) but not at low programming voltages, increasing the fixed program time for the generation and application of all of the charge pump pulses during the programming cycle would also be undesirable since it also increases the total programming time. It is therefore desirable to provide a non-volatile memory system, where the above-described difficulties are alleviated.